Chemical-mechanical polishing (CMP) is used increasingly as a planarizing technique in the manufacture of very large scale integration (VLSI) integrated circuits. It has potential for planarizing a variety of materials in IC processing but is used most widely for planarizing metallizied layers and interlevel dielectrics on semiconductor wafers, and for planarizing substrates for shallow trench isolation. The efficient polishing of copper surfaces has taken on added importance due to the wide spread use of the copper damascene process.
There are three critical consumable components in the CMP process. The first is the abrasive liquid slurry. The abrasive liquid slurry's composition must be altered, and special formulations must be produced for each different substrate being polished. For example, some substrates require a high pH to be activated for polishing, while other substrates need a more acid environment. Still other substrates respond best to silica abrasives, while others require alumina or titanium abrasive particles. The second critical consumable component in the CMP process is the polishing pad. It must be very flat, uniform across its entire surface, and resistant to the chemical nature of the slurry and have the right combination of stiffness and compressibility to minimize effects like dishing and erosion. A third critical consumable component in the CMP process is the carrier film. The carrier film attaches the wafer to its rotating holder must be: adequately flat and uniform in its thickness; an adhesive that will hold it tightly to the carrier but not too tightly to the wafer; and immune to the chemical environment in which it works.
In trench isolation, large areas of field oxide must be polished to produce a planar starting wafer. Integrated circuits that operate with low voltages, i.e., 5 volts or less, and with shallow junctions, can be isolated effectively with relatively shallow trenches, i.e., less than a micron. In shallow trench isolation (STI) technology, the trench is backfilled with oxide and the wafer is planarized using CMP. The result is a more planar structure than typically obtained using LOCOS, and the deeper trench (as compared with LOCOS) provides superior latch up immunity. Also, by comparison with LOCOS, STI substrates have a much reduced “bird's beak” effect and thus theoretically provide higher packing density for circuit elements on the chips. The drawbacks in STI technology to date relate mostly to the planarizing process. Achieving acceptable planarization across the full diameter of a wafer using traditional etching processes has been largely unsuccessful. By using CMP, where the wafer is polished using a mechanical polishing wheel and a slurry of chemical etchant, unwanted oxide material is removed with a high degree of planarity.
It is also well known that integrated circuit fabrication on semiconductor wafers require the formation of precisely controlled apertures, such as contact openings or “vias,” that are subsequently filled and interconnected to create components and VLSI or ultra large scale integration (ULSI) circuits. Equally well known is that the patterns defining such openings are typically created by optical lithographic processes that require precise alignment with prior levels to accurately contact the active devices located in those prior levels. In multilevel metallization processes, each level in the multilevel structure contributes to irregular topography. In three or four level metal processes, the topography can be especially severe and complex. The expedient of planarizing the interlevel dielectric layers, as the process proceeds, is now favored in many state-of-the-art IC processes. Planarity in the metal layers is a common objective, and is promoted by using plug interlevel connections. A preferred approach to plug formation is to blanket deposit a thick metal layer on the interlevel dielectric and into the interlevel windows, and then remove the excess using CMP. In a typical case, CMP is used for polishing an oxide, such as SiO2, Ta2O5, W2O5. It can also be used to polish nitrides such as Si3 N4, TaN, TiN, and conductor materials used for interlevel plugs, e.g., Cu, W, Ti, and TiN.
During conventional metal chemical-mechanical polishing (CMP) of metal stacks, an oxidant is used to convert the top metal to metal oxides. These metal oxides are subsequently abraded in situ with some harder metal oxide abrasives. It certain applications, it is desirable to selectively polish such metal surfaces without removing the underlying nitride surface, for example. In such situations, selective metal polishing and precise end-point detection are desirable features.
During metal CMP, areas dense in features (i.e., alignment marks) tend to oxidize at a faster rate than areas with sparse distributions. This uncontrollable oxidation of the metals forming the alignment marks is commonly referred to as oxide erosion. Additionally, manufacturers have observed that oxide erosion in dense arrays increases dramatically as batch sizes are increased.
Traditionally, polishing pads are composed of stacked polyurethane based materials, containing a softer bottom structure and harder top surface used for polishing. Two examples of such pads in wide commercial use include the IC1400™ and IC1000/SUBAIV™, pads, manufactured by Rodel®, Inc. (Phoenix, Ariz.). Such polyurethane pads, however, are subject to wear down and glazing due to hydrolysis during polishing, with consequent deleterious effects on the rate and uniformity of planarization. This in turn requires frequent reconditioning to restore the pad's surface properties, with a subsequent loss in productivity and increase in costs.
Accordingly, what is needed in the art is an improved design for a semiconductor wafer polishing pad that reduces scratches and resultant yield loss during chemical/mechanical planarization, provides selective metal polishing and end-point detection of such polishing.